1. Field of the Invention
The present invention relates to a package substrate, semiconductor package and fabrication method thereof. More particularly, this invention relates to a package substrate with a cavity, package-on-package and fabrication method thereof.
2. Description of the Prior Art
The need in recent years for increased chip capacity and density with a smaller footprint has led to development of three-dimensional packages and packaging techniques. Three-dimensional packages generally allow smaller, thinner packages and are considered to offer a solution for high packaging density and enhanced electrical performance, which are required for the present and future electronic systems.
One type of three-dimensional packages is Package-on-Package (PoP), which is an integrated circuit packaging technique to allow vertically combining discrete logic and memory ball grid array (BGA) packages. Two or more packages are installed on top of one another, i.e. stacked, with a standard interface to route signals between them. This allows higher density, for example in the mobile telephone market.
FIG. 1 is a schematic, cross-sectional diagram showing a conventional PoP structure. As shown in FIG. 1, the conventional PoP structure 1 comprises a first package 2 and a second package 3 stacked on the first package 2. The first package 2 comprises a first die 20 mounted on a first carrier substrate 22 and the first die 20 is electrically connected to the first carrier substrate 22 through bond wires 26 such as gold wires. The first die 20 and the bond wires 26 are encapsulated by a molding compound 24. The second package 3 comprises a second die 30 mounted on a second carrier substrate 32 and the second die 30 is electrically connected to the second carrier substrate 32 through bond wires 36. Likewise, the second die 30 and the bond wires 36 are encapsulated by molding compound 34. The second carrier substrate 32 of the second package 3 is electrically connected to the first carrier substrate 22 of the first package 2 using solder balls 40. Ordinarily, underfill 42 is applied to fill the gap between the first and second carrier substrates 22 and 32 to prevent solder balls 40 from damage due to stress.
However, the aforesaid conventional PoP structure 1 has several shortcomings. First, the size and dimension of the solder balls 40 are strictly limited to the distance between the first and second carrier substrates 22 and 32. The height of each of the solder balls 40 must exceed the height of the molding compound 24 to ensure reliable electrical connection between the first and second carrier substrates 22 and 32. Therefore, it is difficult to decrease the pitch of the solder balls 40, which leads to restricted number of the I/O pin count. Second, The mismatch of coefficient of thermal expansion (CTE) between the first and second carrier substrates 22 and 32 may lead to concentration of stress on the solder balls 40 and thus affecting reliability of the package. Third, the control of the coplanarity of the solder balls 40 is difficult, which leads to smaller process window.
Further, the prior art PoP package structure needs additional underfill between the first and second carrier substrates 22 and 32 for reliability concern. Furthermore, the prior art PoP package structure occupies larger space.
U.S. Pat. No. 6,625,880 discloses a multi-layer printed wiring board manufactured by forming a wiring pattern and a component mounting portion on a first substrate. An insulating spacer, formed with a first opening, is stacked over the first substrate with the first opening in registration with the component mounting portion. A second substrate is stacked over the spacer and the resulting assembly is bonded together. A second opening, continuing to the first opening, is formed in the second substrate, exposing the component mounting portion to the outside. An LSI is mounted on the component mounting portion, the first and second openings are filled with a synthetic resin mass, and then a third substrate is stacked over the second substrate to enclose the openings.